1. Field of the Invention
The present invention relates to an optical receiver circuit for receiving an RZ-DPSK optical signal and for demodulating it.
2. Description of the Related Art
As a technology for transmitting signals in an optical transmission system, phase modulation has been put to practical use widely. In the phase modulation, data is transmitted by shifting a phase of a carrier wave in accordance with data to be transmitted. In Binary Phase Shift Keying (BPSK) modulation, for example, “θ” and “θ+π” are assigned to data “0” and “1” in each bit, respectively. In Quaternary Phase Shift Keying (QPSK) modulation, “θ”, “θ+π/2”, “θ+π” and “θ+3π/2” are assigned to each symbol comprising 2-bit data, “00”, “01”, “11” and “10”, respectively. Here, “θ” is an arbitrary phase. A receiver apparatus can regenerate the transmitted data by detecting the phase of the received signal.
When increasing transmission speed or distance of a transmission path, deterioration of an optical S/N ratio becomes a problem in the receiver apparatus.
In recent years, research and development of Differential Phase Shift Keying (DPSK) modulation have been making progress as phase modulation, which enables to improve receiver sensitivity. In the DPSK (DBPSK, for example) modulation, the phase of a carrier wave (“θ” or “θ+π”) is determined in accordance with a “change” between a bit value (0 or 1) transmitted previously and a bit value (0 or 1) to be transmitted next. In other words, in demodulating a DPSK signal in the receiver apparatus, data is regenerated by detecting a phase difference between the consecutive two bits.
An RZ (Return to Zero)-DPSK modulation, which further applies intensity modulation to the above DPSK signal in the transmitter apparatus and transmits the signal, is well known. The optical power of an RZ-DPSK signal is set low in a region where the phase of the carrier wave shifts, and thus, signal degradation caused by phase modulation is suppressed.
FIG. 1 is a diagram showing an example of a conventional receiver circuit for demodulating a DPSK signal. In FIG. 1, an interferometer (1-bit delaying interferometer) 101 comprises a 1-bit delaying element on one side of a pair of wave guides, and outputs a pair of optical signals in accordance with the phase difference between the consecutive two bits. A balanced photodiode 102 converts a pair of optical signals output from the interferometer 101 into an intensity-modulated signal. The output signal of the balanced photodiode 102 is amplified by an amplifier 103, and is further converted into an NRZ signal by a low-pass filter 104. Then, “0/1” data is acquired from the NRZ signal by an NRZ data Clock Data Recovery (CDR) circuit 105. RZ-DPSK modulation transmitter circuits and receiver circuits are described in, for example, Patent Documents 1-3. In Patent Document 4, a configuration using a Bang-Bang phase comparator is described as a common embodiment of the CDR circuit 105.
However, the CDR circuit described in Patent Document 4 requires a number of logic circuits and has difficulty in recovering high-speed data faster than 20 Gbps. The CDR circuit described in Patent Document 4, also, is not mass-produced due to its specific usage and therefore, is costly.
FIG. 2 is a diagram showing another example of a conventional receiver circuit for demodulating a DPSK signal. In FIG. 2, an input RZ-DPSK signal is split by an optical power splitter 111, and one is guided to the interferometer 101, and the other is guided to a photodiode 112. Here, the interferometer 101, the balanced photodiode 102, the amplifier 103, and the low-pass filter 104 are basically the same as explained with reference to FIG. 1. The photodiode 112 converts the RZ-DPSK signal into an electrical signal. This electrical signal is amplified by an amplifier 113, and further, its noise is removed by a band-pass filter 114. A flip-flop circuit 115 determines a logical value of the output signal of the low-pass filter 104 using the output signal of the band-pass filter 114 as a clock.
However, in this circuit, it is difficult to adjust to constantly keep the optimal phase difference when the data rate is high because the delay occurring between the optical power splitter 111 and the flip-flop circuit 115 is large. A problem of degradation in receiver sensitivity occurs under the circumstances.
[Patent Document 1]
    Japanese laid-open unexamined patent publication No. 2001-251250 (Japanese Patent No. 3625726)[Patent Document 2]    Japanese laid-open unexamined patent publication No. 2004-254242[Patent Document 3]    US published application No. 2004/0081470[Patent Document 4]    U.S. Pat. No. 5,012,494